A Highly Digital Microbolometer ROIC employing a Novel Event-based Readout and Two-Step Time to Digital Converters

Shahbaz Abbasi
Electronics Engineering, PhD Dissertation, 2019

Thesis Jury

Prof. Dr. Yaşar Gürbüz (Thesis Advisor), Assist. Prof. Dr. Ömer Ceylan, Assist. Prof. Dr. Erdinç Öztürk, Prof. Dr. Uğur Çilingiroğlu, Prof. Dr. Arda Deniz Yalcinkaya

Date & Time: March 25th, 2019 – 10:00 AM

Place: L035 FENS

Keywords : Long-wave infrared, uncooled microbolometer, readout integrated circuit, time-mode processing, low power, NETD, self-heating.

Abstract

Uncooled infrared imaging systems are a light weight and low cost alternative to their cooled counterparts. Uncooled microbolometer IR focal plane arrays (IRFPAs) for applications such as medical imaging, thermography, night vision, surveillance and industrial process control have recently been under focus. These systems have small pixel pitches (< 25 μm) and require power effciency, low noise equivalent temperature difference (NETD) (< 50 mK) and adequate scene dynamic range (> 250 K). Low NETD demands excellent microbolometer and readout noise performance. If sensitive analog circuits, driving long metal interconnects, are part of the pre-digitization readout channel, this necessitates the use of power consuming buffers, potentially in conjunction with noise cancellation circuits that result in power and area overhead. Thus re-thinking at the architectural level is crucial to meet these demands.

Accordingly, in this thesis a column-parallel readout architecture for frame synchronous microbolometer imagers is proposed that enables low power operation by employing a time mode digitizer. The proposed readout circuit is based on a bridge type detector network with active and reference microbolometers and employs a capacitive transimpedance amplifer (CTIA) incorporating a novel two-step integration mechanism. By using a modifed reset scheme in the CTIA, a forward ramp is initiated at the input side followed by the conventional backward integrated ramp at the output. This extends the measurement interval and improves signal-to-noise ratio. A synchronous counter based time-to-digital converter measures this interval providing robust digitization. This technique also provides a way of compensating for self-heating effects.

Being highly digital, the proposed architecture offers robust frontend processing and achieves a per channel power consumption of 66 μW, which is considerably lower than the most recently reported designs, while maintaining better than 10- mK readout NETD.